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pin configuration (top view) general description the hi-8599 from holt integrated circuits is a silicon gate cmos device for interfacing a 16-bit parallel data bus directly to the arinc 429 serial bus. this device provides two receivers, an independent transmitter and line driver capability in a single package. the receiver input circuitry and logic are designed to meet the arinc 429 specifications for loading, level detection, timing, and protocol. the transmitter section provides the arinc 429 communication protocol and the line driver circuits provide the arinc 429 output levels. the 16-bit parallel data bus exchanges the 32-bit arinc data word in two steps when either loading the transmitter or interrogating the receivers. the data bus interfaces with cmos and ttl. the hi-8599 provides the option to bypass most of the internal output resistance so that external series resistance may be added for lighting protection and still match the 75 ohm characteristic impedance of the arinc bus. each independent receiver monitors the data stream with a sampling rate 10 times the data rate. the sampling rate is software selectable at either 1mhz or 125khz. the results of a parity check are available as the 32nd arinc bit. the hi-8599 examines the null and data timings and will reject erroneous patterns. for example, with a 125 khz clock selection, the data frequency must be between 10.4 khz and 15.6 khz. the transmitter has a first in, first out (fifo) memory to store 8 arinc words for transmission. the data rate of the transmitter is software selectable by dividing the master clock, clk, by either 10 or 80. the master clock is used to set the timing of the arinc transmission within the required resolution. the hi-8599 is nearly identical to the hi-8589 but has a test input pin not found in the hi-8589. applications ! ! ! avionics data communication serial to parallel conversion parallel to serial conversion 44-pin plastic quad flat pack (pqfp) (see page 13 for additional pin configurations) 44 - 429di2(a) 43 - 429di1(b) 42 - 429di1(a) 41 - vcc 40 - test 39 - 38 - 37 - 36 - 35 - 34 - mr cwstr txclk clk n/c n/c 33 - 32 - n/c 31-v+ 30 - txb(out) 29 - txa(out) 28-v- 27 - gnd 26 - tx/r 25 - 24 - 23 - entx bd00 pl2 pl1 bd10 - 12 bd09 - 13 bd08 - 14 bd07 - 15 bd06 - 16 gnd-17 bd05 - 18 bd04 - 19 bd03 - 20 bd02 - 21 bd01 - 22 429di2(b) - 1 -2 -3 sel - 4 -5 -6 bd15 - 7 bd14 - 8 bd13 - 9 bd12 - 10 bd11 - 11 d/r1 d/r2 en1 en2 hi-8599pqi & hi-8599pqt june 2012 arinc 429 transmitter with line driver and dual receivers hi-8599 (ds8599 rev.c) 06/12 features ! ! ! ! ! ! ! ! ! ! ! arinc specification 429 compliant direct receiver and transmitter interface to arinc bus in a single device 16-bit parallel data bus timing control 10 times the data rate selectable data clocks receiver error rejection per arinc specification 429 automatic transmitter data timing self test mode parity functions low power industrial & full military temperature ranges holt integrated circuits www.holtic.com
signal function description v power +5v 5% bd05 i/o data bus bd04 i/o data bus bd03 i/o data bus bd02 i/o data bus tx/r output transmitter ready flag. goes low when arinc word loaded into fifo. goes high after transmission and fifo empty. cc v+ power +9.5v to +10.5v v- power -9.5v to -10.5v 429di1 (a) input arinc receiver 1 positive input 429di1 (b) input arinc receiver 1 negative input 429di2 (a) input arinc receiver 2 positive input 429di2 (b) input arinc receiver 2 negative input output receiver 1 data ready flag output receiver 2 data ready flag sel input receiver data byte selection (0 = byte 1) (1 = byte 2) input data bus control, enables receiver 1 data to outputs input data bus control, enables receiver 2 data to outputs if is high bd15 i/o data bus bd14 i/o data bus bd13 i/o data bus bd12 i/o data bus bd11 i/o data bus bd10 i/o data bus bd09 i/o data bus bd08 i/o data bus bd07 i/o data bus bd06 i/o data bus gnd power 0 v bd01 i/o data bus bd00 i/o data bus input latch enable for byte 1 entered from data bus to transmitter fifo. input latch enable for byte 2 entered from data bus to transmitter fifo. must follow . txa(out) output line driver output - a side txb(out) output line driver outpu t - b side entx input enable transmission input clock for control word register clk input master clock input tx clk output transmitter clock equal to master clock (clk), divided by either 10 or 80. input master reset, active low test input disable transmitter output if high (pull-down) d/r1 d/r2 en1 en2 en1 pl1 pl2 pl1 cwstr mr pin description hi-8599 holt integrated circuits 2
v cc v cc gnd gnd 429di1 (b) 429di2 (b) or 429di1 (a) 429di2 (a) or differential amplifiers ones comparators null zeroes figure 1. arinc receiver input data bus function control description pin if enabled, the transmitter?s digital bdo5 self test 0 = enable outputs are internally connected to the receiver logic inputs receiver 1 if enabled, arinc bits 9 and, bdo6 decoder 1 = enable 10 must match the next two control word bits if receiver 1 decoder is bdo7 - - enabled, the arinc bit 9 must match this bit if receiver 1 decoder is bdo8 - - enabled, the arinc bit 10 must match this bit receiver 2 if enabled, arinc bits 9 and bdo9 decoder 1 = enable 10 must match the next two control word bits if receiver 2 decoder is bd10 - - enabled, then arinc bit 9 must match this bit if receiver 2 decoder is bd11 - - enabled, then arinc bit 10 must match this bit invert logic 0 enables normal odd parity bd12 xmtr 1 = enable and logic 1 enables even parity parity output in transmitter 32nd bit bd13 xmtr data 0 = 10 clk is divided either by 10 or clk select 1 = 80 80 to obtain xmtr data clock bd14 rcvr dta 0 = 10 clk is divided either by 10 or clk select 1 = 80 80 to obtain rcvr data clock control word register the hi-8599 contains 10 data flip flops whose d inputs are connected to the data bus and clocks connected to . each flip flop provides options to the user as follows: cwstr the receivers arinc bus interface figure 1 shows the input circuit for each receiver. the arinc 429 specification requires the following detection levels: the hi-8599 guarantees recognition of these levels with a common mode voltage with respect to gnd less than 4v for the worst case condition (4.75v supply and 13v signal level). the tolerances in the design guarantee detection of the above levels, so the actual acceptance ranges are slightly larger. if the arinc signal is out of the actual acceptance ranges, including the nulls, the chip rejects the data. state differential voltage one +6.5 volts to +13 volts null +2.5 volts to -2.5 volts zero -6.5 volts to -13 volts byte 2 data bd bd bd bd bd bd bd bd bd bd bd bd bd bd bd bd bus 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 arinc 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 bit arinc 429 data format the following table shows the bit positions in exchanging data with the receiver or the transmitter. arinc bit 1 is the first bit transmitted or received. data bd bd bd bd bd bd bd bd bd bd bd bd bd bd bd bd bus 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 arinc 13 12 11 10 9 31 30 32 12345678 bit byte 1 functional description (cont.) hi-8599 holt integrated circuits 3
functional description (cont.) hi-8599 sel en d/r decoder control bits / mux control latch enable control 32 to 16 driver 32 bit latch 32 bit shift register to pins control bit bd14 clock option clock clk bit counter and end of sequence parity check 32nd bit data bit clock eos word gap word gap timer bit clock end start sequence control error clock error detection shift register shift register null zeros shift register ones eos bits9&10 figure 2. receiver block diagram receiver logic operation bit timing bit rate pulse rise time pulse fall time pulse width figure 2 is a block diagram showing each receiver?s logic. arinc 429 specifies the following timing for received data: 100k bps 1% 12k -14.5k bps 1.5 0.5 sec 10 5 sec 1.5 0.5 sec 10 5 sec 5 sec 5% 34.5 - 41.7 sec the hi-8581 and hi-8589 accepts signals meeting these specifi- cations and rejects signals outside these tolerances using the method described here: 1. the timing logic requires an accurate 1.0 mhz clock source. less than 0.1% error is recommended. 2. the sampling shift registers are 10 bits long and must show three consecutive ones, zeros or nulls to be consid- ered valid data. to qualify data bits, one or zero in the upper bits of the sampling shift register must be followed by null in the lower bits within the data bit time. a word gap null re- quires three consecutive nulls in both the upper and lower bits of the sampling shift register. this guarantees the mini- mum pulse width. high speed low speed 3. each data bit must follow its predecessor by not less than 8 samples and not more than 12 samples. in this manner the bit rate is checked. with exactly 1 mhz input clock frequency, the acceptable data bit rates are as follows: 83k bps 10.4k bps 125k bps 15.6k bps 4. the word gap timer samples the null shift register every 10 input clocks (80 for low speed) after the last data bit of a valid reception. if the null is present, the word gap counter is incremented. a count of 3 enables the next reception. once 32 valid bits are recognized, the receiver logic generates an end of sequence (eos). if the receiver decoder is enabled and the 9th and 10th arinc bits match the control word program bits or if the receiver decoder is disabled, then eos clocks the data ready flag flip flop to a "1", or (or both) will go low. the data flag for a receiver remains low until after arinc bytes from that receiver are retrieved. this is accomplished by first acti- vating with sel, the byte selector, low to retrieve the first byte and then activating with sel high to retrieve the second byte. retrieves data from receiver 1 and retrieves data from re- ceiver 2. if another arinc word is received and a new eos occurs before the two bytes are retrieved, the data is overwritten by the new word. high speed low speed data bit rate min data bit rate max retrieving data d/r1 d/r2 en en en1 en2 both holt integrated circuits 4
hi-8599 0 data data 1 parity bit 0 = odd parity 1= odd parity error (even parity) cr4 arinc bus fifo 32nd bit 32nd bit error bit: functional description (cont.) receiver parity the receiver parity check enable bit (control register bit 4, cr4) controls how the 32nd bit of the received arinc word is interpreted by the hi-3585 receiver. , the 32nd bit is treated as data and transferred as received from the arinc bus to the receive fifo. , the 32nd bit is treated as a parity error bit. the receiver expects the 32nd bit of the received word to indicate odd parity. if this is the case, the parity bit is reset to indicate correct parity was received and resulting word is written to the receive fifo. if the received word is even parity, the receiver sets the 32nd bit to a ?1?, indicating a parity error. the resulting word is then written to the receive fifo. therefore, when cr4 is set to ?1?, the 32nd bit retrieved from the receiver fifo will always be ?0? when valid (odd parity) arinc 429 words are received. when cr4 is set to a ?0? when cr4 is set to a ?1? odd parity received even parity received transmitter a block diagram of the transmitter section is shown in figure 3. the fifo is loaded sequentially by first pulsing to load byte 1 and then to load byte 2. the control logic automatically loads the 31 bit word in the next available position of the fifo. if tx/r, the transmitter ready flag is high (fifo empty), then 8 words, each 31 bits long, may be loaded. if tx/r is low, then only the available positions may be loaded. if all 8 positions are full, the fifo ignores further attempts to load data. when entx goes high, enabling transmission, the fifo positions are incremented with the top register loading into the data transmission shift register. within 2.5 data clocks the first data bit appears at either txa(out) or txb(out). the 31 bits in the data transmission shift register are presented sequentially to the outputs in the arinc 429 format with the following timing: arinc data bit time 10 clocks 80 clocks data bit time 5 clocks 40 clocks null bit time 5 clocks 40 clocks word gap time 40 clocks 320 clocks the word counter detects when all loaded positions are transmitted and sets the transmitter ready flag, tx/r, high. fifo operation data transmission pl1 pl2 high speed low speed transmitter parity the parity generator counts the ones in the 31-bit word. if the bd12 control word bit is set low, the 32nd bit transmitted will make parity odd. if the control bit is high, the parity is even. if the bd05 control word bit is set low, the digital outputs of the transmitter are internally connected to the logic inputs of the receivers, bypassing the analog bus interface circuitry. data to receiver 1 is as transmitted and data to receiver 2 is the complement. all data transmitted during self test is also present on the txa(out) and txb(out) line driver outputs. taking test high forces txa(out) and txb(out) into the null state regardless of the state of bd05 control word bit. the two receivers are independent of the transmitter. therefore, control of data exchanges is strictly at the option of the user. the only restrictions are: 1. the received data may be overwritten if not retrieved within one arinc word cycle. 2. the fifo can store 8 words maximum and ignores attempts to load addition data if full. 3. byte 1 of the transmitter data must be loaded first. 4. either byte of the received data may be retrieved first. both bytes must be retrieved to clear the data ready flag. 5. after entx, transmission enable, goes high it cannot go low until tx/r, transmitter ready flag, goes high. otherwise, one arinc word is lost during transmission. self test system operation holt integrated circuits 5
figure 3. transmitter block diagram bit bd12 data clock control bit bd13 pl1 pl2 clk tx clk parity generator data and null timer sequencer line driver bit and word gap counter start sequence word counter and fifo control increment word count data clock divider fifo loading sequencer txa(out) txb(out) 8 x 31 fifo 31 bit parallel load shift register bit clock word clock address load data bus tx/r entx test hi-8599 holt integrated circuits 6 functional description (cont.)
line driver operation the line driver in the hi-8599 is designed to directly drive the arinc 429 bus. the two arinc outputs (txa(out) and txb(out)) provide a differential voltage to produce a +10 volt one, a -10 volt zero, and a 0 volt null. setting control register bit 13 to zero causes a slope of 1.5 s on the arinc outputs. a one in control register bit 13 causes a slope of 10 s. timing is set by on-chip resistor and capacitor and tested to be within arinc requirements. he hi-8599 has 10 ohms in series with each line driver output, and is for applications where additional external series resistance is required, such as lightning protection. no additional hardware is required to control the slope. t repeater mode of operation allows a data word that has been received by the hi-8599 to be placed directly into its fifo for transmission. repeater operation is similar to normal receiver operation. in normal operation, either byte of a received data word may be read from the receiver latches first by use of sel input. during repeater operation however, the lower byte of the data word must be read first. this is necessary because, as the data is being read, it is also being loaded into the fifo and the transmitter fifo is always loaded with the lower byte of the data word first. signal flow for repeater operation is shown in the timing diagrams section. the ?-10? version of the hi-8599 product require a 10 kohm resistor to be placed in series with each arinc input without affecting the arinc input thresholds. this option is especially useful in applications where external lightning protection is required. each arinc input pin must be connected to the arinc bus through a 10 kohm resistor in order for the chip to properly detect the correct arinc levels. the typical 10 volt differential signal is translated and input to a window comparator and latch. the comparator levels are set so that with the external 10 kohm resistors, they are just below the standard 6.5 volt minimum arinc data threshold and just above the 2.5 volt maximum arinc null threshold. please refer to the holt an-300 application note for additional information and recommendations on lightning protection of holt line drivers and line receivers. repeater operation hi-8599-10 power supply sequencing the power supplies should be controlled to prevent large currents during supply turn-on and turn-off. the recommended sequence is v+ followed by vcc, always ensuring that v+ is the most positive supply. the v- supply is not critical and can be asserted at any time. data rate - example pattern txa(out) arinc bit txb(out) null data data data null null word gap bit 1 next word bit 32 bit 31 bit 30 loading control word cwhld t cwset t cwstr t data bus cwstr valid timing diagrams functional description (cont.) hi-8599 holt integrated circuits 7
transmitter operation pl2 dwset t dwhld t tx/r t dwhld t pl12 t pl t data bus pl1 tx/r byte 2 valid pl t pl12 t dwset t byte 1 valid transmitting data arinc bit arinc bit pl2 entx txa(out) txb(out) diff v (txa(out) - txb(out)) +5v +5v +5v +10v +10v -10v -5v -5v -5v tx/r pl2en t endat t dtx/r t entx/r t data bit 1 data bit 2 data bit 32 one level zero level null level 90% 90% 10% 10% t fx t rx t fx t rx arinc bit receiver operaton data ready flag d/r arinc data byte select sel enable byte on bus en data bus bit 31 bit 32 selen t d/r t ensel t dataen t d/ren t end/r t en t ensel t selen t dataen t endata t endata t enen t don't care don't care don't care byte 1 valid byte 2 valid timing diagrams (cont.) hi-8599 holt integrated circuits 8
repeater operation timing don't care 429di d/r en pl1 pl2 sel tx/r entx txa(out) txb(out) bit 32 don't care d/r t en t d/ren t enen t en t end/r t selen t ensel t enpl t plen t selen t ensel t enpl t plen t tx/r t tx/ren t endat t entx/r t dtx/r t null t bit 1 bit 32 timing diagrams (cont.) hi-8599 holt integrated circuits 9
vcc = 5v 5%, gnd = 0v, ta = operating temperature range (unless otherwise specified). v+ = 10v , v- = -10v, absolute maximum ratings note: stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not imp lied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. dc electrical characteristics limits parameter conditions unit symbol differential input voltage: one v common mode voltage 6.5 10.0 13.0 v (429di1(a) to 429di1(b); 429di2(a) to 429di2(b)) zero v less than 4v with -13.0 -10.0 -6.5 v null v respect to gnd -2.5 0 2.5 v input resistance: differential r 12 k to gnd r 12 27 k to vcc r 12 27 k input current: input sink i 200 a input source i -450 a input capacitance: differential c 20 pf to gnd c 20 pf to vcc c 20 pf input voltage: input voltage hi v 2.1 v input voltage lo v 0.7 v input current: input sink i 1.5 a input source i -1.5 a pull-down current (test pin) i 50 150 input voltage: input voltage hi v 2.7 v input voltage lo v 0.7 v input current: input sink i 10 a min typ max arinc inputs bi-directional inputs other inputs ih il nul i g h ih il i g h ih il ih il ih il ih (guaranteed but not tested) (429di1(a), 429di1(b), 429di2(a) & 429di2(b)) a pd power dissipation at 25c plastic plcc/pqfp 1.5 w, derate 10mw/ c ceramic j-lead cerquad 1.0 w, derate 7mw/ dc current drain per pin 10ma operating temperature range: (industrial) -40c to +85c (military) -55c to +125c c storage temperature range: -65c to +150c supply voltages vcc -0.3v to +7v v+ +12.5v v- -12.5v voltage at arinc inputs -29v to +29v soldering temperature (leads) 280c for 10 seconds (package) 220c voltage at any other pin -0.3v to vcc +0.3v hi-8599 holt integrated circuits 10
vcc = 5v 5%, v+ = 10v, v- = -10v, gnd = 0v, ta = operating temperature range (unless otherwise specified). dc electrical characteristics (cont.) limits parameter conditions unit symbol output voltage: logic "1" output voltage v i = -1.5ma 2.7 v logic "0" output voltage v i = 2.6ma 0.4 v output current: output sink i v = 0.4v 3.0 ma (bi-directional pins) output source i v = v - 0.4v 1.1 ma output current: output sink i v = 0.4v 2.6 ma (all other outputs) output source i v = v - 0.4v 1.1 ma output capacitance: c 15 pf v 4.75 5.25 v v+ 9.5 10.5 v v- -9.5 -10.5 v v i 20 ma min typ max arinc outputs other outputs operating voltage range operating supply current arinc output voltage one or zero v no load and magnitude at pin 4.50 5.00 5.50 v null v -0.25 0.25 v arinc output current i 80 ma v+ i 16 ma v- i 16 ma dout nout " " " " " " out dd1 ee1 oh oh ol ol ol out oh out cc ol out oh out cc o cc cc cc1 hi-8599 holt integrated circuits 11
limits parameter symbol units min typ max control word timing receiver timing fifo timing transmission timing line driver output timing pulse width - t 80 ns setup - data bus valid to high t 50 ns hold - high to data bus hi-z t 10 ns delay - start arinc 32nd bit to low: high speed t 16 s low speed t 128 s delay - low to low t 0 ns delay - low to high t 200 ns setup - sel to low t 10 ns hold - sel to high t 10 ns delay - low to data bus valid t 50 100 ns delay - high to data bus hi-z t 30 ns pulse width - or t 80 ns spacing - high to next low t 50 ns pulse width - or t 80 ns setup - data bus valid to high t 50 ns hold - high to data bus hi-z t 10 ns spacing - or t 0 ns delay - high to tx/r low t 840 ns spacing - high to entx high t 0 s delay - 32nd arinc bit to tx/r high t 50 ns spacing - tx/r high to entx low t 0 ns line driver transition differential times: high to low t 1.0 1.5 2.0 cwstr cwstr cwstr d/r d/r en en d/r en en en en en1 en2 en en pl1 pl2 pl pl pl1 pl2 pl2 pl2 cwstr cwset cwhld d/r d/r d/ren end/r selen ensel endata dataen en enen pl dwset dwhld pl12 tx/r pl2en dtx/r entx/r fx delay - entx high to txa(out) or txb(out): high speed t 25 s delay - entx high to txa(out) or txb(out): low speed t 200 s (high speed) s low to high t 1.0 1.5 2.0 s (low speed) high to low t 5.0 10 15 s low to high t 5.0 10 15 s delay - low to low t 0 ns hold - high to high t 0 ns delay - tx/r low to entx high t 0 ns t 400 ns 1% endat endat rx fx rx enpl plen tx/ren mr repeater operation timing master reset pulse width arinc data rate and bit timing en pl pl en ac electrical characteristics hi-8599 vcc = 5v, v+ = 10v, v- = -10v, gnd = 0v, ta = operating temp. range and f clock = 1mhz 0.1% with 60/40 duty cycle + holt integrated circuits 12
ordering information hi - 8599 x xxx-xx additional hi-8599 pin configurations 39 entx 38 n/c 37 v+ 36 txb(out) 35 txa(out) 34 v- 33 gnd 32 tx/r 31 30 29 bd00 pl2 pl1 hi-8599pji hi-8599pjt 44-pin plastic j-lead plcc hi-8599cji hi-8599cjt 44-pin j-lead cerquad (see page 1 for the 44-pin plastic quad flat pack (pqfp) pin configuration) 10 ohms part number 8599 output series resistance built-in required externally 27.5 ohms package description 44 pin plastic j lead plcc (44j) 44 pin cerquad j lead (44u) not available pb-free part number pj cj 44 pin plastic quad flat pack, pqfp (44pqs) pq temperature range flow burn in -40c to +85c no i -55c to +125c no t part number t i 100% matte tin (pb-free, rohs compliant) f tin / lead (sn / pb) solder blank part number lead finish input series resistance built-in required externally part number 25 kohm -10 35 kohm no dash number 10 kohm 0 429di2(b) 7 8 9 sel 10 11 12 bd15 13 bd14 14 bd13 15 bd12 16 bd11 17 d/r1 d/r2 en1 en2 39 entx 38 n/c 37 v+ 36 txb(out) 35 txa(out) 34 v- 33 gnd 32 tx/r 31 30 29 bd00 pl2 pl1 bd10 18 bd09 19 bd08 20 bd07 21 bd06 22 gnd 23 bd05 24 bd04 25 bd03 26 bd02 27 bd01 28 6 429di2(a) 5 429di1(b) 4 429di1(a) 3 vcc 2 test 1 44 txclk 43 clk 42 n/c 41 n/c 40 mr cwstr 429di2(b) 7 8 9 sel 10 11 12 bd15 13 bd14 14 bd13 15 bd12 16 bd11 17 d/r1 d/r2 en1 en2 bd10 18 bd09 19 bd08 20 bd07 21 bd06 22 gnd 23 bd05 24 bd04 25 bd03 26 bd02 27 bd01 28 6 429di2(a) 5 429di1(b) 4 429di1(a) 3vcc 2 test 1 44 txclk 43 clk 42 n/c 41 n/c 40 mr cwstr hi-8599 holt integrated circuits 13
revision history p/n rev date description of change ds8599 c 06/29/12 added revision history page. updated pqfp package drawing. clarified the description of receiver parity. updated minimum input voltage hi for other inputs. hi-8599 holt integrated circuits 14
hi-8599 package dimensions 44-pin plastic plcc inches (millimeters) package type: 44j bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) pin no. 1 ident .045 x 45 .045 x 45 pin no. 1 .173 .008 (4.394 .203) .690 .005 (17.526 .127) sq. .610 .020 (15.494 .508) .031 .005 (.787 .127) .653 .004 (16.586 .102) sq. .017 .004 (.432 .102) .050 (1.27) bsc detail a r .010 .001 (.254 .03) .020 (.508) min see detail a .035 .010 (.889 .254) 44-pin j-lead cerquad inches (millimeters) package type: 44u bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) 2 1 44 43 .620 .012 (15.748 .305) .688 .005 (17.475 .127) .650 .010 (16.510 .254) sq. .200 (5.080) max .050 (1.270) .019 .002 (.483 .051) .100 .007 (2.540 .178) bsc .039 .005 (.990 .127) sq. max holt integrated circuits 15
hi-8599 package dimensions package type: 0 7 detail a see detail a sq. 44pmqs 44-pin plastic quad flat pack (pqfp) .009 (.23) .520 .010 (13.20 .25) .394 .004 (10.0 .10) sq. max. .014 .003 (.37 .08) .035 .006 (.88 .15) .005 (.13) r min. .012 (.30) r max. .079 .008 (2.0 .20) .096 (2.45) max. .0315 (.80) inches (millimeters) bsc bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) holt integrated circuits 16

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